Can some kind person sum up what his problem with core-rope memory is? I'm not up for suffering through his grating voice while waiting for him to get to the point.
He often invents spurious design "rules" violated by the system in question. He's never able to explain where the rules come from or to derive them from basic physics. His only real justification is that he's never seen things done that way anywhere else, and besides it comes from NASA so it can't possibly work.
Basically, it's a lack of imagination coupled with limited experience and knowledge that makes him think he knows much more than he does. Few things are more dangerous.
The key element of the core rope memory, which I didn't understand when I first looked at it, is magnetic saturation. Unlike read-write core memory, where individual cores retain a magnetized state encoding a 0 or a 1, core rope memory cores are "soft" -- they do not remain magnetized when the external field is removed. They are actually transformer cores whose degree of magnetization follows the strength of the current in the wire(s) running through them. But like all magnetic materials, you can magnetize them only so far; once all the little domains are pointing in the same direction, you can't point any more and core magnetization stops rising. The core saturates, and as long as it remains saturated any further changes in the applied magnetic field no longer induce a voltage in other wires running through it. (A transformer can induce a voltage only when the magnetic field in its core is changing.)
This is the key to the core rope memory. Each address line is provided in inverted and non-inverted form, i.e., there are two wires for each address bit, one carrying current when the address bit is a '1' and the other carrying current when the bit is a '0'. They are all weaved through the cores in such a way that every core has at least one wire carrying current
except the one being addressed.
The current in each address line is strong enough to saturate the magnetic core material, inhibiting its ability to couple (act as a transformer) a pulse in a readout query wire to a sense wire. The query wire runs through every core, but the sense wire either goes through a core or around it, depending on whether a '1' or a '0' is encoded at that location. (The data is literally woven into the rope.) The sense wire then goes to an amplifier to detect the pulse, if present.
Again, the key feature is magnetic saturation. The only core able to act as a transformer to couple the readout pulse to the sense wire is the one with no current through any of its address lines, and there's only one of those for any given address. A core with one or more active address lines saturates and is inhibited. In other words, it forms a multi-input NOR (negative OR) gate without using any semiconductors.
To me this was the really clever part. It would have taken thousands of ordinary logic gates to decode the address lines. That's easy today but not in the 1960s when every integrated circuit in the AGC contained just two 3-input NOR gates.
Of course this technique has long been obsolete, and because hunchbacked has never seen it anywhere else he insists it can't work here.
